4-1 tm an9813.1 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 operation of the HC5503C, hc5503t family of slics evaluation board (hc5503xeval1) features one evaluation board for performance testing of the HC5503C, hc5503j and hc5503t family of slics includes on-board op amp and cross point switch for evaluation of ?unctor?applications monitoring of switch hook detect (shd) via on board led automatic on/off controller for cross point switch connection functional description evaluation board to facilitate testing of all 3 parts on one evaluation board, the board is equipped with one double pole double throw (dpdt) toggle switch s 1 . the dpdt switch determines the connection of the slic s transmit (tx) and receive (rx) outputs. the outputs are either connected to banana jacks tx or rx for full evaluation of the voice and dc feeding characteristics (reference figure 4) or the onboard op amp and cross point switch for evaluation of the end-to-end application (reference figure 6). the HC5503C/j/t evaluation board is con?ured to match a 600 ? line impedance via the tip and ring feed resistors r b1 , r b2 , r b3 and r b4 . provided with the evaluation board are two generic hc5503x samples. HC5503C the HC5503C is a low cost subscriber line interface circuit (slic), that replaces the components of an unbalanced discrete analog circuit design. hc5503j the hc5503j is a low cost subscriber line interface circuit (slic), that replaces discrete or thick ?m hybrid ?unctor unbalanced design solutions [1]. hc5503t the hc5503t is a low cost subscriber line interface circuit (slic), that replaces the components of a discrete transformer analog circuit design. power requirements for the HC5503C/j/t power supply connections the HC5503C/j/t evaluation board requires three external power supplies. the slic is powered by two supplies v bat = -48v (typ) and v cc = +5v. the third supply (v ee = -5v) powers the external op amps and cross point switch for the junctor application. ground connections the HC5503C/j/t evaluation board has tied the analog, digital and battery grounds to a common ground plane designated gnd. it is recommended that the analog, digital and battery grounds of the slic be tied together as close to the device pins as possible. the three external power supplies should each be grounded to the evaluation board. getting started verify that the sample is oriented in its socket correctly. correct orientation is with pin 1 pointing towards the onboard pin 1 designator located in the upper left hand corner of the sockets. (reference the data sheet for location of device pin 1.) verifying basic slic operation the operation of the sample parts can be veri?d by performing 4 tests: 1. power supply current veri?ation. 2. normal loop feed veri?ation. 3. tip and ring voltage veri?ation. 4. gain veri?ation (4-wire to 2-wire). the above 4 tests require the following equipment: a 600 ? load, a sine wave generator, an ac volt meter and two external supplies (v bat , v cc ). application tip: when terminating tip and ring, it is handy to assemble terminators using a pomona mdp dual banana plug connector as the terminating resistor receptacle. refer to figure 1 for details. using the termination shown in figure 1 provides an unobtrusive technique for terminating tip and ring while still providing access to both signals using the banana jack feature of the mdp connector. posts are also available that ? into holes a and b, providing a solderable connection for the terminating resistor. test #1 power supply current veri?ation a quick check of evaluation board and the sample is to measure the supply currents. the readings should be similar to the values listed in table 1. the measurements can be made using a series ammeter on each supply, or power supplies with current displays. discussion the currents measured include those of the slic and supporting circuitry (i.e., 2nd hc5503x slic, op amp, gnd ab figure 1. termination adapter 600 ? application note november 1998
4-2 channel a s led, the cross point switch and transistors q 1 and q 2 ). for slic supply currents consult the applicable data sheet. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and ground the v ee pin (v ee supply not required for this test). 3. set the dpdt switch (s1) to standard operation. this connects the transmit and receive outputs to banana jacks tx and rx. 4. terminate tip and ring channel a with a 600 ? load (channel b is disconnected during standard operation). 5. measure the supply currents and compare to those in table 1. test #2 normal loop feed veri?ation this test verifies loop current operation and loop current detection via the onboard led. discussion when power is applied to the slic a loop current will ?w from tip to ring through the 600 ? load. loop current detection occurs when this loop current triggers an internal detector that pulls the output of shd low, illuminating the led through the +5v supply. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and ground the v ee pin (v ee supply not required for this test). 3. set the dpdt switch (s1) to standard operation. this connects the transmit and receive outputs to banana jacks tx and rx. 4. terminate tip and ring channel a with a 600 ? load (channel b is disconnected during standard operation). veri?ation: 1. the shd led is on when tip and ring are terminated with 600 ? . 2. the shd led is off when tip and ring are an open circuit. test #3 tip and ring voltage veri?ation this test veri?s the tip and ring voltages. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and ground the v ee pin (v ee supply not required for this test). 3. set the dpdt switch (s1) to standard operation. this connects the transmit and receive outputs to banana jacks tx and rx. 4. terminate tip and ring channel a with a 600 ? load (channel b is disconnected during standard operation). 5. measure tip and ring voltages with respect to ground and compare to those in table 2. test #4 gain veri?ation (4-wire to 2-wire) this test will verify the slic is operating properly and that the 4-wire to 2-wire gain is 1.0 or 0.0db. discussion when terminated with 600 ? load, the slic will exhibit unity gain from the rx input pin to across tip and ring (vtr). when an open circuit exists, a mismatch occurs and the tip to ring voltage doubles. the db gain is calculated in equation 1. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and ground the v ee pin (v ee supply not required for this test). 3. set the dpdt switch (s1) to standard operation. this connects the transmit and receive outputs to banana jacks tx and rx. 4. terminate tip and ring channel a with a 600 ? load (channel b is disconnected during standard operation). 5. connect a sine wave generator, referenced to ground, to the rx input. 6. set the generator for 1v rms at 1khz. 7. connect an ac voltmeter across tip and ring. veri?ation 1. tip to ring ac voltage of 1v rms when terminated. 2. tip to ring ac voltage of 2v rms when not terminated. verifying junctor operation the operation of the junctor application circuit using the 2 hc5503x samples provided can be veri?d by performing 4 tests: 1. channel to channel transhybrid balance. 2. inter-channel transhybrid balance. 3. channel to channel gain. 4. intra-channel transhybrid balance with different loads. the above 4 tests require the following equipment: two 600 ? loads, a sine wave generator, an ac volt meter and three external supplies (v bat , v cc , v ee ). de?ition of junctor circuit the function of the junctor application circuit is to convert a two port network with a transmit output (tx) and a receive input (rx) into a one-port network. the conversion to a one-port network now makes it easy to connect phone lines in a small pbx or key system through a single cross point. this table 1. HC5503C, hc5503j, hc5503t supply rl ( ? ) typ (ma) v cc = +5v 600 10.9 v bat = -48v 600 33.5 table 2. battery tip typ (v) ring typ (v) v bat = -48v -12.8 -30.6 db 20 v tr v rx ----------- log = (eq. 1) application note 9813
4-3 conversion is accomplished by the connection of a differential amplifier and a summing amplifier. the differential amplifier and summing amplifier are used to cancel the return signal and prevent echo (reference figure 6). in this one-port network, echo can occur in two ways: channel to channel and intra- channel. reference figure 5 for signal path for both channel- to-channel and intra-channel signals. test #5 channel to channel transhybrid de?ition the removal of the receive signal from the transmit signal, to prevent an echo on the transmit side is de?ed as channel to channel transhybrid balance. in other words, channel to channel transhybrid signals occur when the receive signal (from channel b) is retransmitted along with the transmit signal of channel a back to channel b. channel to channel transhybrid balance is performed by the summing ampli?r (the output of this ampli?r is sum a and sum b in figure 6). setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and v ee to -5v. 3. set the dpdt switch (s1) to junctor operation. this connects the onboard op amp, cross point switch and the second hc5503x slic to the transmit and receive outputs of channel a. 4. terminate tip and ring of both channel a and channel b with a 600 ? load. 5. connect a sine wave generator in parallel with the 600 ? load across tip and ring of channel a. the output of this generator needs to be ?ating. 6. set the generator for 1v rms at 1khz. 7. connect an ac volt meter between test point diff b and ground. this will measure the ac voltage at the output to the differential ampli?r (diff b). 8. connect an ac volt meter between test point sum b and ground. this will measure the ac voltage at the output of the summing ampli?r (sum b). 9. the channel to channel transhybrid balance is calculated using the following formula in equation 2. 10. to measure channel to channel transhybrid balance on channel a, connect the sine wave generator in parallel with the 600 ? load across tip and ring of channel b and repeating steps 7 through 9 in a similar fashion. voltage measurements taken at diff a and sum a. results for both channels should be the same. 11. compare results to that listed in table 3. test #6 intra-channel transhybrid de?ition intra-channel transhybrid balance is de?ed as the removal of the transmit signal from the receive signal, and thereby cancellation of echo, within a channel. in other words, intra- channel transhybrid balance is when the transmit signal from channel a is feed back into the input of channel a. intra-channel transhybrid balance is performed by the differential ampli?r (the output of this ampli?r is diff a and diff b in figure 6). calculation of resistor value (r 4 ) for optimum intra-channel transhybrid balance is discussed in test #8. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and v ee to -5v. 3. set the dpdt switch (s1) to junctor operation. this connects the onboard op amp, cross point switch and the second hc5503x slic to the transmit and receive outputs of channel a. 4. terminate tip and ring of both channel a and channel b with a 600 ? load. 5. connect a sine wave generator in parallel with the 600 ? load across tip and ring of channel a. the output of this generator needs to be ?ating. 6. set the generator for 1v rms and 1khz. 7. connect an ac volt meter between test point sum a and ground. this will measure the ac voltage at the input to the differential ampli?r (sum a). 8. connect an ac volt meter between test point diff a and ground. this will measure the ac voltage at the output of the differential ampli?r (diff a). 9. the inter-channel transhybrid balance is calculated using the following formula in equation 3. 10. to measure inter-channel transhybrid balance on channel b, connect the sine wave generator in parallel with the 600 ? load across tip and ring of channel b and repeating steps 7 through 9 in a similar fashion. voltage measurements taken at sum b and diff b. results for both channels should be the same. 11. compare results to that listed in table 3. test #7 channel a to channel b gain this demo board is con?ured to have a channel to channel gain of 1 or 0db. this test will illustrate a procedure for calculating the proper r 4 resistor value to achieve a channel db 20 sumb diffb ------------------ - log = (eq. 2) table 3. test sum typ (v rms ) diff typ (v rms ) transhybrid balance (db) channel to channel transhybrid balance channel a to b channel b to a 18.45m 20.79m 1.009 1.007 -34.7 -33.7 intra-channel transhybrid balance channel a channel b 0.986 0.990 64.9m 67.0m -23.6 -23.4 db 20 diffa suma ------------------ - log = (eq. 3) application note 9813
4-4 to channel gain of 1 with any cross point or network used to connect the two line cards. also included is an easy procedure to verify the calculations. discussion channel to channel gain is dependent upon: the 2-wire to 4-wire and the 4-wire to 2-wire gains of the hc5503x being one, the gain setting resistors of the differential ampli?r (r 4 , r 5 , r 14 , and r 15 ), the resistance of the cross point switch (rx) and resistors r 6 and r 16 (reference figure 5). the resistance values of r 6 and r 16 are generally set to 604 ? for impedance matching to a transformer line card. if impedance matching to a 600 ? transformer is not a design requirement, then the values of r 6 and r 16 are not critical and can be set to match various impedances. it is important however, that r 6 equal r 16 . figure 2 is a simpli?d version of the junctor circuit and shows the critical components required to calculate the optimum r 14 value to obtain a channel a to channel b gain of one. because the 2-wire to 4-wire gain of the hc5503x is one, the voltage appearing at v1 is the tip to ring voltage of channel a (summing ampli?r con?ured for a gain of one). the tip to ring voltage of channel b is equal to the voltage at vo, because the 4-wire to 2-wire gain of the hc5503x is also one. writing an equation for vo in terms of v1 will enable the gain to be set to one and the corresponding resistor values determined. equation 4 can be used to determine the output voltage of the differential ampli?r, and therefore the tip to ring voltage of channel b, in terms of the voltage at v2. the voltage at v2, with respect to v1, is: substituting equation 5 into equation 4 and de?ing r x =r x + r 10 . where r x is the total network resistance connecting junctor a and junctor b input/outputs. dividing both sides by v1 yields an equation for channel a to channel b gain. setting v0/v1 equal to one and rearranging to solve for r 14 , assuming r 6 = r 16 , yields equation 8. equation 8 can be used for the calculation of r 14 to achieve a channel a to channel b gain of one. a similar analysis for the calculation of r 4 to achieve a channel b to channel a gain of one is given in equation 9. the value of r 14 and r 4 can now be determined for any network resistance. the network resistance is defined as the total resistance between the junctor inputs/outputs. in the case of the demo board the network resistance is the resistance of the cross point switch (50 ? ) and r 10 (100 ?) .if r 1 = r 11 = r 2 = r 12 = r 5 = r 15 = 10k ? , r 6 =r 16 = 604 ? and the network = 150 ? then r 4 = 12.48k ? . closest standard value is 12.7k ?. if the network resistance is equal to 50 ? (single cd22m3493 cross point), then r 4 = 10.83k ?. closest standard value is 10.7k ? . veri?ation the following procedure can be used to verify the above calculations. setup 1. connect the power supplies to the evaluation board. 2. set v bat to -48v, v cc to +5v and v ee to -5v. 3. set the dpdt switch (s1) to junctor operation. this connects the onboard op amp, cross point switch and the second hc5503x slic to the transmit and receive outputs of channel a. 4. terminate tip and ring of both channel a and channel b with a 600 ? load. vo v2 1 r 14 r 15 --------- - + ?? ?? ?? = (eq. 4) v2 r 16 r 6 r x r 10 r 16 ++ + ------------------------------------------------------- ?? ?? ?? v1 = (eq. 5) vo v1 r 16 r 6 r x r 16 ++ ---------------------------------------- ?? ?? ?? 1 r 14 r 15 --------- - + ?? ?? ?? = (eq. 6) vo v1 -------- - channelb channela ----------------------------- r 16 r 6 r x r 16 ++ ---------------------------------------- ?? ?? ?? 1 r 14 r 15 --------- - + ?? ?? ?? == (eq. 7) r 14 r 15 1 r x r 6 --------- - + ?? ?? ?? = (eq. 8) r 4 r 5 1 r x r 6 --------- - + ?? ?? ?? = (eq. 9) + - + - r 2 r 6 junc a -5v 5v -5v 5v + - r 16 junc b -5v 5v 150 ? figure 2. channel to channel transhybrid balance vo transmit output of channel b is zero channel b channel a v2 600 ? 600 ? r 6 600 ? 50 ? v1 v2 differential amplifier r 1 10k ? 10k ? 10k ? r 5 10k ? r 15 12.7k ? r 14 r 12 10k ? r 11 10k ? v1 x point r 10 100 ? r 16 600 ? network r x r x r 10 r x = r x + r 10 application note 9813
4-5 5. connect a sine wave generator in parallel with the 600 ? load across tip and ring of channel a. the output of this generator needs to be ?ating. 6. set the generator for 1v rms and 1khz. 7. measure the ac voltage across tip and ring (vtr) of both channels a and b. 8. the channel a to channel b gain is calculated using the following formula in equation 10. 9. to measure channel b to channel a gain connect the sine wave generator in parallel with the 600 ? load across tip and ring of channel b and repeating steps 7 and 8 in a similar fashion. results for both channels should be about the same. 10. compare results to that listed in table 4. test #8 intra-channel transhybrid balance with different loads this evaluation board is con?ured to give the optimum intra-channel transhybrid balance for an impedance of 150 ? between the two junctor inputs/outputs. this test will illustrate a procedure for calculating the proper r 4 and r 14 resistor values to optimize the intra-channel transhybrid balance when a different cross point or network is used. also included is an easy procedure to verify the calculations. discussion intra-channel transhybrid balance is performed by the differential amplifier (reference figure 3). the goal is to cancel all of the transmit signal of channel a by the differential amplifier, so that none of the transmit signal is feed back into the receive terminal of channel a. the transmit signal can be cancelled by the differential amplifier by adjusting the value of resistor r 4 . the value of r 4 is dependent upon: the resistance value of r 6 , the resistance of the network that connects the two junctor inputs/outputs together (cross point + r 10 ) and resistor r 16 . figure 3 is a simplified version of the junctor circuit and shows the critical components required to calculate the optimum r 4 value for intra-channel transhybrid balance. equation 11 is the characteristic equation for the output voltage of the differential ampli?r. the voltage at v2, with respect to v1, where r x = resistance of cross point switch is: substituting equation 12 into equation 11, setting v0 equal to zero, defining r x = r x + r 10 and rearranging to solve for r4: equation 13 can be used for the calculation of r 4 to achieve a good intra-channel transhybrid balance in channel a. a similar analysis for channel b is given in equation 14. the value of r 4 and r 14 can now be determined for any network resistance. in the case of the demo board, the network resistance (r x ) is the resistance of the cross point switch (50 ? ) and r10 (100 ?) . if r 1 =r 11 =r 2 = r 12 =r 5 =r 15 = 10k ? ,r 6 =r 16 = 604 ? and the network = 150 ? then r 4 = 12.48k ? . closest standard value is 12.7k ?. if the network resistance is equal to 50 ? (single cd22m3493 cross point), then r 4 = 10.83k ?. closest standard value is 10.7k ?. notice that the calculated value of r 4 and r 14 for both channel to channel and intra-channel are the same. this is because the gain from channel to channel is set for one. if the channel to channel gain was set to anything other than one, the intra-channel transhybrid balance would become unacceptable. proper operation of this circuit requires that the channel to channel gain be set to one. table 4. test tip to ring channel a (v rms ) tip to ring channel b (v rms ) gain (db) channel a to channel b gain 1.0074 1.0063 -0.01 channel b to channel a gain 1.0035 1.0068 -0.03 db 20 vtr channelb () vtr channela () ---------------------------------------------- log = (eq. 10) vo v1 1 r 4 r 5 ------ - + ?? ?? ?? v2 r 4 r 5 ------ - = (eq. 11) v2 r x r 10 r 16 ++ r x r 10 r 16 r 6 +++ ------------------------------------------------------- ?? ?? ?? v1 = (eq. 12) r 4 r 5 r x r 16 + () r 16 --------------------------------------- = (eq. 13) r 14 r 15 r x r 6 + () r 6 --------------------------------------- - = (eq. 14) junc a + - r 12 r 16 junc b -5v 5v figure 3. intra-channel transhybrid balance transmit output of channel b is zero channel b v2 600 ? r 6 600 ? v1 v2 + - -5v 5v + - r 6 -5v 5v vo 600 ? differential amplifier 10k ? r 5 12.7k ? r 4 r 2 10k ? r 1 10k ? v1 channel a 50 ? x point r 10 100 ? r 16 600 ? network r x r 10 r x = r x + r 10 150 ? r x application note 9813
4-6 veri?ation the following procedure can be used to verify the above calculations. setup 1. replace resistors r 4 and r 14 with a 10.7k ? resistor as calculated above. note, r 14 is channel b s equivalent of channel a s r 4 . 2. connect the power supplies to the evaluation board. 3. set v bat to -48v, v cc to +5v and v ee to -5v. 4. set the dpdt switch (s 1 ) to junctor operation. this connects the onboard op amp, cross point switch and the second hc5503j slic to the transmit and receive outputs of channel a. 5. replace resistor r 10 with a short. this will result in a network resistance of 50 ? total. 6. terminate tip and ring of both channel a and channel b with a 600 ? load. 7. connect a sine wave generator in parallel with the 600 ? load across tip and ring of channel a. the output of this generator needs to be ?ating. 8. set the generator for 1v rms and 1khz. 9. connect an ac volt meter between test point sum a and ground. this will measure the ac voltage at the input to the differential ampli?r (sum a). 10. connect an ac volt meter between test point diff a and ground. this will measure the ac voltage at the output of the differential ampli?r (diff a). 11. the intra-channel transhybrid balance is calculated using the following formula in equation 15. 12. to measure intra-channel transhybrid balance on channel b, connect the sine wave generator in parallel with the 600 ? load across tip and ring of channel b and repeating steps 8 through 11 in a similar fashion. voltage measurements taken at sum b and diff b. results for both channels should be the same. 13. compare results to that listed in table 3 section ?ntra-channel transhybrid balance. functional circuit component descriptions a brief description of each component is provided below. the components will be grouped by function to provide further insight into the operation of the HC5503C/j/t board. reference [1] hc5503j - future product. for more information call don lafontaine at (321) 729-5604. table 5. two wire side, tip and ring r b1 , r b2 , r b3 , r b4 , r b5 , r b6 , r b7 , r b8 feed resistors (r b1 ,r b2 ,r b3 ,r b4 ,r b5 ,r b6 , r b7 and r b8 ) that set the 2-wire impedance to 600 ? .r b2 ,r b4 ,r b6 and r b8 are used for loop current detection. r b1 ,r b3 ,r b5 and r b7 are used for current limiting during a surge event. d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 secondary surge protection. db 20 diffa suma ------------------ - log = (eq. 15) table 6. junctor circuit ca324e intersil quad op amp. r 1 , r 2 , r 3 , r 11 , r 12 , r 13 transhybrid balance and gain setting resistors for the summing ampli?rs. r 4 , r 5 , r 14 , r 15 transhybrid balance and gain setting resistors for the differential ampli?rs. c 8 ,c 17 ,c 25 , c 26 , c 23 , c 24 compensation capacitors to roll of the high fre- quency gain of the summing and differential am- pli?r. c 23 and c 24 prevent a dc loop. r 6 , r 16 provides a 600 ? termination looking into the junctor input. r 10 series resistor to bring the total resistance of the ?etwork to 150 ? . the ?etwork is defined as the total resistance that connects junctor a to junctor b. c 4 , c 5 , c 6 , c 7 , c 21 , c 22 ac decoupling capacitors for the hc5503x trans- mit (tx) and receive (rx) outputs. cdm22m3493 cross point switch. the resistance of the switch (x0 to y0) is approximately 50 ?. s 1 dpdt switch used to connect the slic s transmit and receive outputs of channel a to either banana jacks tx and rx or the onboard op amp and cross point for evaluation of the junctor circuit. q 1 , q 2 , r 7 , r 8 , r 9 , d 9 automatic on/off controller of the cross point switch. this circuit senses the shd outputs of both slics. if both slics are in the off-hook condition, then the cross point switch is activated and the junctor a and junctor b outputs are connected together. if either slic is in the on-hook condition, the cross point switch is off and junctor a and junctor b outputs are disconnected. table 7. filter capacitor c 1 , c 18 c 1 and c 18 are required for proper operation of the slic s loop current limit function. table 8. supply decoupling capacitors c 2 , c 3 , c 9 -c 16 , c 19 , c 20 supply decoupling capacitors. table 9. shd leds r 9 ,r 20 ,d 9 , d 10 r 9 and r 20 are the current limiting resistors for the shd leds (d 9 and d 10 ). table 10. pullup resistors r 17 , r 19 pull up resistors (r 17 , r 19 ). required for proper operation of the slic. application note 9813
4-7 schematic diagram for standard operation r b4 ring vb(int) / rf tip v bat hc5503x r b2 r b1 ring r b3 channel a -48v 1 8 9 2 tip feed tip rx tx t3 t2 t1 c1 v bat bgnd dgnd agnd v cc shd 12 10 11 5 21 c 3 3 v cc c 2 pin numbers given for 22 pin dip c 1 22 19 18 17 16 4 c 7 c 6 6 5v 1k 510 rx tx s 1 standard operation figure 4. application schematic for standard operation u1 r 17 r 18 d 11 rs channel b hc5503 junctor cross point switch junctor channel a hc5503 path for intra-channel transhybrid path for channel-to-channel transhybrid figure 5. intra-channel and channel-to-channel paths through the system HC5503C/j/t evaluation board parts list component value tolerance rating component value tolerance rating slic u1 u2 hc5503x hc5503x c 2 , c 19 0.01 f 20% 100v quad op amp u3 ca324e c 3 , c 20 0.01 f 20% 50v cross point switch u4 cd22m3493 c 4 , c 5 , c 6 , c 7 , c 21 , c 22 0.47 f 20% 50v r 1 ,r 2 ,r 3 ,r 5 ,r 9 ,r 11 , r 12 , r 13 , r 15 10k ? 1% 1/4w c 8 , c 17 , c 25 , c 26 .001 f 10% 50v r b1 , r b2 , r b3 , r b4 , r b5 , r b6 , r b7 , r b8 150 ? 1% 2w c 23 , c 24 0.82 f 20% 50v r 8 5.62k ? 1% 1/4w c 9 , c 11 , c 13 , c 15 supply decoupling 0.1 f 10% 50v r 4 , r 14 12.7k ? 1% 1/4w c 10 , c 12 , c 14 , c 16 supply decoupling 0.01 f 10% 50v r 6 , r 16 604 ? 1% 1/4w d 1 ,d 2 ,d 3 ,d 4 ,d 5 ,d 6 ,d 7 , d 8 , d 11 1n40007 n/a 100v, 1a r 18 , r 20 510 ? 5% 1/4w d 9 , d 10 led, red r 7 , r 17 , r 19 1.0k ? 5% 1/4w s 1 spdt co pc mount switch c 1 , c 18 0.33 f 10% 50v r10 100 ? 1% 1/4w application note 9813
4-8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com schematic diagram for junctor application r b4 ring vb(int) / rf tip slic r b2 r b1 ring r b3 ch a -48v 1 8 9 2 tip feed tip rx tx t3 t2 t1 c 1 vbat bgnd dgnd agnd v cc shd 12 10 11 5 21 c 3 3 v cc c 2 rs c 1 22 19 18 17 16 4 c 5 c 4 6 5v 1k 510 s 1 junctor operation r b8 ring vb(int) / rf tip slic r b6 r b5 ring r b7 ch b -48v 1 8 9 2 tip feed tip rx tx t3 t2 t1 c 1 v bat bgnd dgnd agnd v cc shd 12 10 11 5 21 c 20 3 v cc c 19 rs c 18 22 19 18 17 16 4 6 5v 1k 510 + - + - r 3 r 1 r 2 r 4 r 5 r 6 c 8 c 22 c 21 diff a sum a diff b sum b cd22m3493 cross point switch junc a u1 u2 data strobe reset v cc v ss -5v 5v -5v 5v -5v 5v x0 y0 ax0 ax1 ax2 ax3 ay 0 ay 1 ay 2 -5v figure 6. application schematic for junctor operation hc5503x d 10 d 11 r 17 r 19 r 20 r 18 ca324e quad op amp u3 u4 d 1 d 2 d 3 d 4 pin numbers given for 22 pin dip hc5503x -5v 5v automatic on/off r 7 r 8 r 9 c 25 c 24 + - + - r 13 r 11 r 12 r 14 r 15 r 16 c 17 junc b -5v 5v -5v 5v c 26 c 23 q 1 q 2 c 9 c 10 c 11 c 12 c 15 c 16 c 13 c 14 d 9 r 10 v bat controller d 5 d 6 d 7 d 8 v bat application note 9813
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